Many computerized systems, such as portable computers, are battery operated and measures are taken to reduce their power consumption. One method used to reduce power consumption is shutting down units which are not currently in use. The unit which is shut down generally disables its clock and waits for a signal instructing it to wake up, i.e., to enter an active mode.
US patent publication 2008/0178026 to Chen, titled: “Computer System and Power Saving Method Thereof”, the disclosure of which is incorporated herein by reference, describes a system in which when a chipset and a processor are in a power saving mode a bus connecting the chipset and processor is disabled. When the chipset needs to send data to the processor it enables the bus, transmits the data and then moves back to the sleep state.
EP patent 1 594 253 to Bogavac Davor, titled: “Method and Device to Wake-up Nodes in a Serial Databus”, the disclosure of which is incorporated herein by reference, describes another system with nodes that wake up responsive to transmissions from a master unit, each unit waking up only for specific transmissions directed to it.
The waking up process may take time, referred to as a “wake up latency”. In some cases, the source of transmitted data is not aware that the receiving unit is asleep and the sleeping unit is configured to wake up immediately when it identifies that signals are being transmitted on the bus. If the wake up latency is not sufficiently short, however, the sleeping unit will wake up only after at least part of the data from the source was transmitted and the transmission will be lost. While some sources may be configured to receive retransmission requests, other sources may not be so adapted and the data they transmit is permanently lost if the receiving unit does not awake fast enough.
U.S. Pat. No. 7,363,523 to Kurts et al., titled: “Method and Apparatus for Controlling Power Management State Transitions”, the disclosure of which is incorporated herein by reference, suggests having a plurality of low power states for a processor, involving different extents of processor units shut down. When a bus signal is received, the processor does not move to a full scale operation state, but rather moves to an intermediate operation state which is sufficient to handle the bus access. The transition to the intermediate state is performed within 35 microseconds.
U.S. Pat. No. 7,039,819 to Kommrusch et al., titled: “Apparatus and Method for Initiating a Sleep State in a System on a Chip Device”, the disclosure of which is incorporated herein by reference, suggests a state having a wake latency of about 1 microsecond.
Some processors, however, may not be able to wake up with a short enough latency, to catch the beginning of data transmitted on the bus.
US patent publication 2007/0239920 to Frid, titled: “Method and System for Communication Between a Secondary Processor and an Auxiliary Display Subsystem of a Notebook”, the disclosure of which is incorporated herein by reference, suggests including a low power auxiliary display in a portable computer, which can be used instead of waking up the main processor and display of the computer. This solution, however, still requires substantial power amounts for the auxiliary display, and it would be desired to have a sleep state also for the auxiliary display in order to further reduce power consumption.
U.S. Pat. No. 6,892,332 to Gulick, titled: “Hardware Interlock Mechanism Using a Watchdog Timer”, the disclosure of which is incorporated herein by reference, describes a system in which wake-ups are performed periodically and not responsive to external signals. Such a system is susceptible both to unnecessary wake ups and to delayed responses to external requests.